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HD6417618 Datasheet(PDF) 529 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 529 Page - Renesas Technology Corp |
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529 / 646 page  Section 19 User Debugging Interface (H-UDI) Rev. 6.00 Jun. 12, 2007 Page 497 of 610 REJ09B0131-0600 Table 19.2 H-UDI Commands Bits 15 to 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description 0 0 0 0 JTAG EXTEST 0 0 1 0 JTAG CLAMP 0 0 1 1 JTAG HIGHZ 0 1 0 0 JTAG SAMPLE/PRELOAD 0 1 1 0 H-UDI reset, negate 0 1 1 1 H-UDI reset, assert 1 0 1 H-UDI interrupt 1 1 1 0 JTAG IDCODE (Initial value) 1 1 1 1 JTAG BYPASS Other than above Reserved 19.3.3 Boundary Scan Register (SDBSR) SDBSR is a 333-bit shift register, located on the PAD, for controlling the input/output pins of this LSI. The initial value is undefined. This register cannot be accessed by the CPU. Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 19.3 shows the correspondence between this LSI's pins and boundary scan register bits. |
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