HD6417618 datasheet(527/646 Pages) RENESAS

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Section 19 User Debugging Interface (H-UDI)

Rev. 6.00 Jun. 12, 2007 Page 495 of 610

REJ09B0131-0600

19.2

Input/Output Pins

Table 19.1 shows the pin configuration of the H-UDI.

Table 19.1

Pin Configuration

Abbr.

Input/Output

Description

TCK

Input

Serial Data Input/Output Clock Pin

Data is serially supplied to the H-UDI from the data input pin

(TDI) and output from the data output pin (TDO) in

synchronization with this clock.

TMS

Input

Mode Select Input Pin

The state of the TAP control circuit is determined by changing

this signal in synchronization with TCK. The protocol conforms

to the JTAG standard (IEEE Std.1149.1).

TRST

Input

Reset Input Pin

Input is accepted asynchronously with respect to TCK, and

when low, the H-UDI is reset.

TRST must be low for the given

period when the power is turned on regardless of using the H-

UDI function. This is different from the JTAG standard.

For details on resets, see section 19.4.2, Reset Configuration.

TDI

Input

Serial Data Input Pin

Data transfer to the H-UDI is executed by changing this signal

in synchronization with TCK.

TDO

Output

Serial Data Output Pin

Data read from the H-UDI is executed by reading this pin in

synchronization with TCK. The data output timing depends on

the command type set in SDIR. For details, see section 19.3.2,

Instruction Register (SDIR).

ASEMD

Input

ASE Mode Select Pin

When a low level is input to the

ASEMD pin, ASE mode is

entered; if a high level is input, normal mode is entered. In ASE

mode, the emulator functions can be used. The input level on

the

ASEMD pin should be held unchanged except during the

RES pin assertion period.

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