HD6417618 datasheet(415/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 383 of 610

REJ09B0131-0600

14.5

SCIF Interrupts

The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),

receive-data-full (RXI), and break (BRI).

Table 14.11 shows the interrupt sources and their order of priority. The interrupt sources are

enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt

request is sent to the interrupt controller for each of these interrupt sources.

When TXI request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR) is

set to 1, a TXI interrupt request is generated.

When RXI request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXI

interrupt request is generated. The RXI interrupt request caused by DR flag is generated only in

asynchronous mode.

When BRI request is enabled by RIE bit or REIE bit and the BRK flag in SCFSR or ORER flag in

SCLSR is set to 1, a BRI interrupt request is generated.

When ERI request is enabled by RIE bit or REIE bit and the ER flag in SCFCR is set to 1, an ERI

interrupt request is generated.

When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERI interrupt and BRI

interrupt without requesting RXI interrupt.

The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that

there is receive data in SCFRDR.

Table 14.11 SCIF Interrupt Sources

Interrupt

Source

Description

Interrupt

Enable Bit

Priority on

Reset Release

ERI

Interrupt initiated by receive error (ER)

RIE or REIE

High

RXI

Interrupt initiated by receive data FIFO full (RDF) or

data ready (DR)

RIE

BRI

Interrupt initiated by break (BRK) or overrun error

(ORER)

RIE or REIE

TXI

Interrupt initiated by transmit FIFO data empty

(TDFE)

TIE

Low

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