HD6417618 datasheet(391/646 Pages) RENESAS

391 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 359 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

SCKDT

*

R/W

SCK Port Data

Controls the SCK pin in combination with the SCKIO bit

in this register, the C/

A bit in SCSMR, and bits CKE1

and CKE0 in SCSCR. Select the SCK pin function in

the PFC (pin function controller) beforehand.

A CKE1 CKE0 SCKIO SCKDT: SCK pin state

×:

Input (initial state)

Low level output

High level output

×:

Internal clock output

according to serial core

logic

×:

External clock input to

serial core logic

×:

Setting prohibited

×:

Internal clock output

according to serial core

logic

×:

Internal clock output

according to serial core

logic

×:

External clock input to

serial core logic

×:

Setting prohibited

×: Don't care

The SCK pin state is read from this bit instead of the

set value.

SPBIO

R/W

Serial Port Break Input/Output Control

Controls the TxD pin in combination with the SPBDT bit

in this register and the TE bit in SCSCR.

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