HD6417618 datasheet(387/646 Pages) RENESAS

387 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 355 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

MCE

R/W

Modem Control Enable

Enables modem control signals

CTS and RTS.

In synchronous mode, clear this bit to 0.

This bit is available only in SCFCR_0 and SCFCR_1. In

SCFCR_2, this bit is reserved. The initial value is 0 and

the write value should always be 0.

0: Modem signal disabled*

1: Modem signal enabled

Note: * The

CTS signal is fixed active 0 regardless of

the input value, and the

RTS signal is also

fixed 0.

TFRST

R/W

Transmit FIFO Data Register Reset

Disables the transmit data in the transmit FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * Reset operation is executed by a power-on

reset.

RFRST

R/W

Receive FIFO Data Register Reset

Disables the receive data in the receive FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * Reset operation is executed by a power-on

reset.

LOOP

R/W

Loop-Back Test

Internally connects the transmit output pin (TxD) and

receive input pin (RxD) and enables loop-back testing.

0: Loop back test disabled

1: Loop back test enabled

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