34708 datasheet(148/159 Pages) FREESCALE

148 / 159 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

148

MC34708

Typical Applications

8.3

MC34708 Layout Guidelines

8.3.1

General board recommendations

1. It is recommended to use an 8 layer board stack-up arranged as follows:

• High current signal

•GND

•Signal

• Power

•Signal

•GND

• High current signal

2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.

3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

8.3.2

Component Placement

Sense resistors should be placed as Close to the IC as possible. Route the high current path flowing from VBATT to BATTISNSN

as thick and as short as possible to reduce power losses.

8.3.3

General Routing Requirements

1. Some recommended things to keep in mind for manufacturability:

• Via in pads require a 4.5 mil Minimum annular ring. Pad must be 9.0 mils larger than the hole

• Max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper

• Minimum allowed spacing between line and hole pad is 3.5 mils

• Minimum allowed spacing between line and line is 3.0 mils

2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from

power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins.

3. Shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the

ground and power planes shield these traces).

4. Sense pins must be directly connected to the 0.02 Ohm sense resistor R1 (BATTISNSN and BATTISNSP).

5. Avoid coupling trace between important signal/low noise supplies (like VREFCORE, VCORE, VCOREDIG) from any

switching node (i.e. SW1ALXx, SW2LXx, SW3LXx, SW4ALX, SW4BLX, SW5LXx and SWBSTLXx).

6. Make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all

components related to the SW1 converter must referenced to GNDSW1A1 and GNDSW1A2.

8.3.4

Parallel Routing Requirements

1. SPI/I2C signal routing:

• CLK is the fastest signal of the system, so it must be given special care. Here are some tips for routing the communication

signals:

• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to

shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole

signal trace length.

34708 Datasheet(PDF) 148 Page - Freescale Semiconductor, Inc

34708 Datasheet(HTML) 148 Page - Freescale Semiconductor, Inc

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