HD6417618 datasheet(317/646 Pages) RENESAS

317 / 646 page

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 285 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

TFP1

TFP0

R/W

Transmit Frame Position 1, 0

These two bits specify the relationship between the

transmit buffer and transmit frame. In the preceding

and following descriptors, a logically positive

relationship must be maintained between the settings

of this bit and the TDLE bit.

00: Frame transmission for transmit buffer indicated

by this descriptor continues (frame is not

concluded)

01: Transmit buffer indicated by this descriptor

contains end of frame (frame is concluded)

10: Transmit buffer indicated by this descriptor is start

of frame (frame is not concluded)

11: Contents of transmit buffer indicated by this

descriptor are equivalent to one frame (one

frame/one buffer)

TFE

R/W

Transmit Frame Error

Indicates that one or other bit of the transmit frame

status indicated by bits 26 to 0 is set. Whether or not

the transmit frame status information is copied into

this bit is specified by the transmit/receive status copy

enable register.

0: No error during transmission

1: An error occurred during transmission

26 to 0

TFS26 to

TFS0

All 0

R/W

Transmit Frame Status

TFS26 to TFS4: Reserved (The write value should

always be 0.)

TFS3: Carrier Not Detect (corresponds to CND bit in

EESR)

TFS2: Detect Loss of Carrier (corresponds to DLC bit

in EESR)

TFS1: Delayed collision Detect (corresponds to CD

bit in EESR)

TFS0: Transmit Retry Over (corresponds to TRO bit

in EESR)

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