HD6417618 datasheet(244/646 Pages) RENESAS

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Section 9 Watchdog Timer (WDT)

Rev. 6.00 Jun. 12, 2007 Page 212 of 610

REJ09B0131-0600

H'5A

Write data

Address: H'F815FF84

WTCNT write

H'A5

Write data

Address: H'F815FF86

WTCSR write

Figure 9.2 Writing to WTCNT and WTCSR

9.3

WDT Operation

9.3.1

Canceling Software Standbys

The WDT can be used to cancel software standby mode with an NMI interrupt or external

interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used

for canceling, so keep the

RES pin low until the clock stabilizes.)

1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When

the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the

count overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in WTCNT. These values should ensure that the time till count overflow is longer

than the clock oscillation settling time.

3. Move to software standby mode by executing a SLEEP instruction to stop the clock.

4. The WDT starts counting by detecting the change of input levels of the NMI or IRQ pin.

5. When the WDT count overflows, the CPG starts supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set when this happens.

6. Since the WDT continues counting from H'00, set the STBY bit in STBCR to 0 in the interrupt

processing program and this will stop the WDT to count. When the STBY bit remains 1, the

LSI again enters software standby mode when the WDT has counted up to H'80. This software

standby mode can be canceled by a power-on reset.

HD6417618 Datasheet(PDF) 244 Page - Renesas Technology Corp