HD6417618 datasheet(209/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 177 of 610

REJ09B0131-0600

CKIO

A25 to A0

CSn

RD/

Tpw

Trr

Trc

Hi-z

Trc

CKE

RAS

DQMxx

CAS

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.24 Self-Refreshing Timing

Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus

cycle execution, the refresh cycle must wait for the bus cycle to be completed.

If a new refresh request occurs while the previous refresh request is not performed, the previous

refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the

bus busy must be prevented.

Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed

after turning the power on. To perform synchronous DRAM initialization correctly, the BSC

registers must first be set, followed by writing to the synchronous DRAM mode register. When

writing to the synchronous DRAM mode register, the address signal value at that time is latched

by a combination of the

CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, write to

the address of X + (H'F8FD5000) in words. In this operation, the data is ignored. To set burst

read/single write, burst read/burst write, CAS latency 2 to 3, wrap type = sequential, and burst

length 1 supported by the LSI, arbitrary data is written to the addresses shown in table 7.14 in

bytes. In this case, 0s are output at the external address pins of A12 or later.

HD6417618 Datasheet(PDF) 209 Page - Renesas Technology Corp