HD6417618 datasheet(208/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 176 of 610

REJ09B0131-0600

2. Self-refreshing

When self-refreshing mode is selected, the refresh timing and refresh addresses are generated

within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit

and the RFSH bit in SDCR to 1. After starting the self-refreshing, the PALL command is

issued in the Tp cycle after the completion of pre-charging the bank. The SELF command is

then issued after inserting idle cycles of which the number is specified by bits WTRP1 and

WTRP0 in CSnWSR. Synchronous DRAM cannot be accessed while self-refreshing.

Self-refreshing mode is cleared by clearing the RMODE bit to 0. After self-refreshing mode

has been cleared, command issuance is disabled for the number of cycles specified by bits

WTRC1 and WTRC0 in CSnWCR.

Self-refreshing timing is shown in figure 7.24. Settings must be made immediately after

clearing self-refreshing mode so that auto-refreshing is performed at the correct intervals.

When self-refreshing is activated from the auto-refreshing mode, only clearing the RMODE bit

to 1 resumes auto-refreshing mode. If it takes long time to start the auto-refreshing, setting

RTCNT to the value of RTCOR

− 1 starts the auto-refreshing immediately.

After self-refreshing has been set, the self-refreshing mode continues even in standby mode,

and is maintained even after recovery from standby mode by an interrupt.

Since the BSC registers are initialized at a power-on reset, the self-refreshing mode is cleared.

HD6417618 Datasheet(PDF) 208 Page - Renesas Technology Corp