HD6417618 datasheet(135/646 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev. 6.00 Jun. 12, 2007 Page 103 of 610

REJ09B0131-0600

Table 6.3

Interrupt Response Time

Number of Cycles

Item

NMI, H-UDI

IRQ, Peripheral

Modules

Remarks

Interrupt priority decision

and comparison with mask

bits in SR

× Icyc + 2 × Pcyc 1 × Icyc + 3 × Pcyc

Wait for completion of

sequence currently being

executed by CPU

X (

≥ 0)

X (

≥ 0)

The longest sequence

is for interrupt or

address-error

exception handling (X =

× Icyc + m1 + m2

+ m3 + m4). If an

interrupt-masking

instruction follows,

however, the time may

be even longer.

Time from start of interrupt

exception handling until

fetch of first instruction of

exception handling routine

starts

× Icyc + m1 + m2

+ m3

× Icyc + m1 + m2

+ m3

Performs the saving

PC and SR, and vector

address fetch.

Interrupt

response

time

Total:

× Icyc + 2 × Pcyc

+ m1 + m2 + m3

+ X

× Icyc + 3 × Pcyc

+ m1 + m2 + m3

+ X

Minimum*:

× Icyc +

× Pcyc

× Icyc +

× Pcyc

SR, PC, and vector

table are all in on-chip

RAM, or cache hit

occurs (in write back

mode).

Maximum:

× Icyc +

× Pcyc + 2 ×

(m1

+ m2 + m3) +

× Icyc +

× Pcyc + 2 ×

(m1

+ m2 + m3) +

Notes: *

In the case that m1 = m2 = m3 = m4 = 1

× Icyc.

m1 to m4 are the number of cycles needed for the following memory accesses.

m1: SR save (longword write)

m2: PC save (longword write)

m3: Vector address read (longword read)

m4: Fetch first instruction of interrupt service routine

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