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HD6417618 Datasheet(PDF) 614 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 614 Page - Renesas Technology Corp |
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614 / 646 page  Section 21 Electrical Characteristics Rev. 6.00 Jun. 12, 2007 Page 582 of 610 REJ09B0131-0600 21.4.9 HIF Timing Table 21.12 HIF Timing Conditions: V CCQ = 3.0 V to 3.6 V, VCC = 1.4 V to 1.6 V, T a = –20°C to +75°C (regular specifications), T a = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Reference Figures Read bus cycle time t HIFCYCR 4 t pcyc Figure 21.40 Write bus cycle time t HIFCYCW 4 t pcyc Address setup time (HIFSCR.DMD = 0) t HIFAS 10 ns Address setup time (HIFSCR.DMD = 1) t HIFAS 0 ns Address hold time (HIFSCR.DMD = 0) t HIFAH 10 ns Address hold time (HIFSCR.DMD = 1) t HIFAH 0 ns Read low width (read) t HIFWRL 2.5 t pcyc Write low width (write) t HIFWWL 2.5 t pcyc Read/write high width t HIFWRWH 2.0 t pcyc Read data delay time t HIFRDD 2 × t pcyc + 16 ns Read data hold time t HIFRDH 0 ns Write data setup time t HIFWDS t pcyc + 10 ns Write data hold time t HIFWDH 10 ns HIFINT output delay time t HIFITD 20 ns Figure 21.41 HIFRDY output delay time t HIFRYD 10 t pcyc Figure 21.42 HIFDREQ output delay time t HIFDQD 20 ns Figure 21.41 HIF pin enable delay time t HIFEBD 20 ns Figure 21.42 HIF pin disable delay time t HIFDBD 20 ns Notes: 1. t pcyc indicates the period of the peripheral module clock (Pφ). 2. t HIFAS is given from the start of the time over which both the HIFCS and HIFRD (or HIFWR) signals are low levels. 3. t HIFAH is given from the end of the time over which both the HIFCS and HIFRD (or HIFWR) signals are low levels. 4. t HIFWRL is given as the time over which both the HIFCS and HIFRD signals are low levels. 5. t HIFWWL is given as the time over which both the HIFCS and HIFWR signals are low levels. 6. When reading the register specified by bits REG5 to REG0 after writing to the HIF index register (HIFIDX), t HIFWRWH (min.) = 2 × tpcyc + 5 ns. |
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