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HD6417618 Datasheet(PDF) 612 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 612 Page - Renesas Technology Corp |
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612 / 646 page ![]() Section 21 Electrical Characteristics Rev. 6.00 Jun. 12, 2007 Page 580 of 610 REJ09B0131-0600 21.4.7 SCIF Timing Table 21.10 SCIF Timing Conditions: V CCQ = 3.0 V to 3.6 V, VCC = 1.4 V to 1.6 V, T a = –20°C to +75°C (regular specifications), T a = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Reference Figures Clocked synchronous 12 t pcyc Figures 21.37 and 21.38 Input clock cycle Asynchronous t Scyc 4 t pcyc Input clock rising time t SCKR 0.8 t pcyc Figure 21.37 Input clock falling time t SCKF 0.8 t pcyc Input clock pulse width t SCKW 0.4 0.6 t Scyc Transmit data delay time t TXD 3 × t pcyc* + 50 ns Figure 21.38 Receive data setup time (clocked synchronous) t RXS 3 t pcyc Receive data hold time (clocked synchronous) t RXH 3 t pcyc RTS delay time t RTSD 100 ns CTS setup time (clocked synchronous) t CTSS 100 ns CTS hold time (clocked synchronous) t CTSH 100 ns Note: * t pcyc indicates the period of the peripheral module clock (Pφ). tSCKW tSCKR tSCKF tScyc SCK Figure 21.37 SCK Input Clock Timing |
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