HD6417618 datasheet(496/646 Pages) RENESAS

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Section 17 I/O Ports

Rev. 6.00 Jun. 12, 2007 Page 464 of 610

REJ09B0131-0600

17.4

Port D

Port D of this LSI is an I/O port with eight pins as shown in figure 17.4.

PD0 (input/output)/RQ0 (input)

PD1 (input/output)/IRQ1 (input)

PD2 (input/output)/IRQ2 (input)/TxD1 (output)

PD3 (input/output)/IRQ3 (input)/RxD1 (input)

PD4 (input/output)/IRQ4 (input)/SCK1 (input/output)

PD5 (input/output)/IRQ5 (input)/TxD2 (output)

PD6 (input/output)/IRQ6 (input)/RxD2 (input)

PD7 (input/output)/IRQ7 (input)/SCK2 (input/output)

Port B

Figure 17.4 Port D

17.4.1

Port D is an 8-bit I/O port that has a following register. For details on the address of this register

and the states of this register in each processing state, see section 20, List of Registers.

• Port D data register L (PDDRL)

17.4.2

Port D Data Register L (PDDRL)

PDDRL is a 16-bit readable/writable register which stores data for port D. Bits PD7DR to PD0DR

correspond to pins PD7 to PD0. (Description of multiplexed functions is omitted.)

When the pin function is general output port, if the value is written to PDDRL, the value is output

from the pin; if PDDRL is read, the value written to the register is directly read regardless of the

pin state.

When the pin function is general input port, not the value of register but pin state is directly read if

PDDRL is read. Data can be written to PDDRL but no effect on the pin state. Table 17.4 shows

the reading/writing function of the port D data register L.

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