HD6417618 datasheet(480/646 Pages) RENESAS

480 / 646 page

Section 16 Pin Function Controller (PFC)

Rev. 6.00 Jun. 12, 2007 Page 448 of 610

REJ09B0131-0600

16.1.9

Port E IO Register H and L (PEIORH and PEIORL)

PEIORH and PEIORL are 16-bit readable/writable registers that select the input/output directions

of the port E pins. Bits PE24IOR to PE0IOR correspond to pins PE24 to PE00 (the pin name

abbreviations for multiplexed functions are omitted). PEIORH is enabled when a port E pin

functions as a general input/output (PE24 to PE16), otherwise, disabled. PEIORL is enabled when

a port E pin functions as a general input/output (PE15 to PE00), otherwise, disabled.

Setting a bit in PEIORH and PEIORL to 1 makes the corresponding pin function as an output and

clearing a bit in PEIORH and PEIORL to 0 makes the pin function as an input.

Bits 15 to 9 in PAIORH are reserved. These bits are always read as 0. The write value should

always be 0.

The initial values of PEIORH and PEIORL are H'0000.

16.1.10

Port E Control Register H1, H2, L1, and L2 (PECRH1, PECRH2, PECRL1, and

PECRL2)

PECRH1, PECRH2, PECRL1, and PECRL2 are 16-bit readable/writable registers that select the

pin functions for the multiplexed port E pins.

• PECRH1

Bit

Bit Name

Initial Value

R/W

Description

15 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PE24MD1

PE24MD0

(non-HIF

boot mode)

(HIF boot

mode)

R/W

PE24 Mode

Selects the function of pin PE24/HIFD15/CTS1.

00: PE24 input/output (port)

01: HIFD15 input/output (HIF)

10: CTS1 input (SCIF)

11: Setting prohibited

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