HD6417618 datasheet(377/646 Pages) RENESAS

377 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 345 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

R/(W)* Receive Data Ready

Indicates that the number of data in the receive FIFO

data register (SCFRDR) is less than the specified

receive trigger number, and that the next data has not

yet been received after the elapse of 15 ETU from the

last stop bit in asynchronous mode. In clock

synchronous mode, this bit is not set to 1.

0: Receiving is in progress, or no receive data

remains in SCFRDR after receiving ended normally

[Clearing conditions]

• DR is cleared to 0 when the chip undergoes a

power-on reset

• DR is cleared to 0 when all receive data are read

after 1 is read from DR and then 0 is written

1: Next receive data has not been received

[Setting conditions]

• DR is set to 1 when SCFRDR contains less data

than the specified receive trigger number, and the

next data has not yet been received after the

elapse of 15 ETU from the last stop bit.*

Note: * This is equivalent to 1.5 frames with the 8-bit,

1-stop-bit format. (ETU: elementary time unit)

Note: *

The only value that can be written is 0 to clear the flag.

HD6417618 Datasheet(PDF) 377 Page - Renesas Technology Corp