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HD6417618 Datasheet(PDF) 339 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 339 Page - Renesas Technology Corp |
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339 / 646 page  Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 6.00 Jun. 12, 2007 Page 307 of 610 REJ09B0131-0600 However, as stated in step 3, the read access to the transmit FIFO by the EtherC module will have been terminated, and the E-DMAC thus stops operating with the transmit FIFO full. In short, this problem arises when [initial value of RP – WP value < length of remaining frame data] at the point of the transmit underflow. Maximum transmit FIFO capacity Transmit FIFO Data for transmission is written by the E-DMAC. Data for transmission is read by EtherC 1. Initial state after software reset WP Minimum transmit FIFO capacity RP Transmit FIFO Transmit FIFO is full Increment Increment 2. Writing and reading of the data for transmission WP RP: Transmit FIFO read pointer WP: Transmit FIFO write pointer RP Maximum transmit FIFO capacity Transmit FIFO Initial state 3. Transmit-FIFO underflow has occurred Minimum transmit FIFO capacity WP RP RP Data for transmission is written by the E-DMAC. Data for transmission is read by EtherC Transmit FIFO 4. Point where the problem makes the E-DMAC stop WP RP Reading of data for transmission by EtherC is terminated. Figure 12.11 Operation when E-DMAC Stops and the Transmit FIFO |
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