CY8C3865LTI-059 datasheet(102/129 Pages) CYPRESS

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PSoC® 3: CY8C38 Family

Data Sheet

Document Number: 001-11729 Rev. *R

Page 102 of 129

11.3.7 USB

11.3.8 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

Note

45. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 79.

Table 11-56. USB DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

VUSB_5

Device supply for USB operation

USB configured, USB regulator

enabled

4.35

–

5.25

VUSB_3.3

USB configured, USB regulator

bypassed

3.15

–

3.6

VUSB_3

USB configured, USB regulator

bypassed[45]

2.85

–

3.6

IUSB_Configured Device supply current in device

active mode, bus clock and IMO =

24 MHz

VDDD = 5 V, FCPU = 1.5 MHz

–

VDDD = 3.3 V, FCPU = 1.5 MHz

–

IUSB_Suspended Device supply current in device

sleep mode

VDDD = 5 V, connected to USB

host, PICU configured to wake on

USB resume signal

–0.5

–

VDDD = 5 V, disconnected from

USB host

–0.3

–

VDDD = 3.3 V, connected to USB

host, PICU configured to wake on

USB resume signal

–0.5

–

VDDD = 3.3 V, disconnected from

USB host

–0.3

–

Table 11-57. UDB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

FMAX_TIMER Maximum frequency of 16-bit timer in

a UDB pair

–

67.01

MHz

FMAX_ADDER Maximum frequency of 16-bit adder in

a UDB pair

–

67.01

MHz

FMAX_CRC

Maximum frequency of 16-bit

CRC/PRS in a UDB pair

–

67.01

MHz

PLD Performance

FMAX_PLD

Maximum frequency of a two-pass

PLD function in a UDB pair

–

67.01

MHz

Clock to Output Performance

tCLK_OUT

Propagation delay for clock in to data

out, see Figure 11-66.

25 °C, Vddd

≥ 2.7 V

–

tCLK_OUT

Propagation delay for clock in to data

out, see Figure 11-66.

Worst-case placement, routing,

and pin selection

––

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