HD6417618 datasheet(178/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 146 of 610

REJ09B0131-0600

7.5.2

Normal Space Interface

Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of

the fact that mainly static RAM will be directly connected. When using SRAM with a

byte-selection pin, see section 7.5.6, Byte-Selection SRAM Interface. Figure 7.3 shows the basic

timings of normal space access. A no-wait normal access is completed in two cycles. The

signal is asserted for one cycle to indicate the start of a bus cycle.

CKIO

RD/

CSn

WEn(BEn)

Read

Write

Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)

There is no output signal which informs external devices of the access size when reading.

Although the least significant bit of the address indicates the correct address when the access

starts, 16-bit data is always read from a 16-bit device. When writing, only the

WEn (BEn) signal

for the byte to be written to is asserted.

HD6417618 Datasheet(PDF) 178 Page - Renesas Technology Corp