HD6417618 datasheet(173/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 141 of 610

REJ09B0131-0600

7.5

Operation

7.5.1

Endian/Access Size and Data Alignment

This LSI supports big endian, in which the most significant byte (MSByte) of multiple byte data is

stored in the lower address, and little endian, in which the least significant byte (LSByte) of

multiple byte data is stored in the lower address. Endian is specified at a power-on reset by the

external pin (MD5). When pin MD5 is driven low at a power-on reset, the endian will become big

endian and when pin MD5 is driven high at a power-on reset, the endian will become little endian.

Two data bus widths (8 bits and 16 bits) are available for normal memory and byte-selection

SRAM. Only 16-bit data bus width is available for SDRAM. Two data bus widths (8 bits and 16

bits) are available for PCMCIA interface. Data alignment is performed in accordance with the data

bus width of the device and endian. This also means that when longword data is read from a

byte-width device, the read operation must be done four times. In this LSI, data alignment and

conversion of data length is performed automatically between the respective interfaces.

HD6417618 Datasheet(PDF) 173 Page - Renesas Technology Corp