HD6417618 datasheet(108/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 76 of 610

REJ09B0131-0600

5.6

Cases when Exceptions are Accepted

When an exception other than resets occurs during decoding the instruction placed in a delay slot

or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in

table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the

exception is accepted.

Table 5.10

Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions

Exception

Occurrence Timing

Address

Error

General

Illegal

Instruction

Slot Illegal

Instruction

Trap

Instruction

Interrupt

Instruction in delay slot

×*2



×*2



×*3

Immediately after interrupt

disabled instruction*

√

×*4

[Legend]

√: Accepted

×: Not accepted

: Does not occur

Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L

2. An exception is accepted before the execution of a delayed branch instruction.

However, when an address error or a slot illegal instruction exception occurs in the

delay slot of the RTE instruction, correct operation is not guaranteed.

3. An exception is accepted after a delayed branch (between instructions in the delay slot

and the branch destination).

4. An exception is accepted after the execution of the next instruction of an interrupt

disabled instruction (before the execution two instructions after an interrupt disabled

instruction).

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