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HD6417618 Datasheet(PDF) 547 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 547 Page - Renesas Technology Corp

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Section 20 List of Registers
Rev. 6.00 Jun. 12, 2007 Page 515 of 610
REJ09B0131-0600
Register Name
Abbreviation
No. of Bits
Address
Module
Access Size
Delayed collision detect counter
register
CDCR
32
H'FB000184
EtherC
32
Lost carrier counter register
LCCR
32
H'FB000188
EtherC
32
Carrier not detect counter register
CNDCR
32
H'FB00018C
EtherC
32
CRC error frame receive counter
register
CEFCR
32
H'FB000194
EtherC
32
Frame receive error counter register
FRECR
32
H'FB000198
EtherC
32
Too-short frame receive counter
register
TSFRCR
32
H'FB00019C
EtherC
32
Too-long frame receive counter
register
TLFRCR
32
H'FB0001A0
EtherC
32
Residual-bit frame counter register
RFCR
32
H'FB0001A4
EtherC
32
Multicast address frame receive
counter register
MAFCR
32
H'FB0001A8
EtherC
32
IPG setting register
IPGR
32
H'FB0001B4
EtherC
32
Automatic PAUSE frame set register
APR
32
H'FB0001B8
EtherC
32
Manual PAUSE frame set register
MPR
32
H'FB0001BC
EtherC
32
PAUSE frame retransfer count set
register
TPAUSER
32
H'FB0001C4
EtherC
32
Break data register B
BDRB
32
H'FFFFFF90
UBC
32
Break data mask register B
BDMRB
32
H'FFFFFF94
UBC
32
Break control register
BRCR
32
H'FFFFFF98
UBC
32
Execution times break register
BETR
16
H'FFFFFF9C
UBC
16
Break address register B
BARB
32
H'FFFFFFA0
UBC
32
Break address mask register B
BAMRB
32
H'FFFFFFA4
UBC
32
Break bus cycle register B
BBRB
16
H'FFFFFFA8
UBC
16
Branch source register
BRSR
32
H'FFFFFFAC UBC
32
Break address register A
BARA
32
H'FFFFFFB0
UBC
32
Break address mask register A
BAMRA
32
H'FFFFFFB4
UBC
32
Break bus cycle register A
BBRA
16
H'FFFFFFB8
UBC
16
Branch destination register
BRDR
32
H'FFFFFFBC UBC
32
Cache control register 1
CCR1
32
H'FFFFFFEC Cache
32
Notes: 1. The numbers of access cycles are eight bits when reading and 16 bits when writing.
2. Supported only by the SH7618A.



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