HD6417618 datasheet(491/646 Pages) RENESAS

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Section 17 I/O Ports

Rev. 6.00 Jun. 12, 2007 Page 459 of 610

REJ09B0131-0600

17.2

Port B

Port B of this LSI is an I/O port with 14 pins as shown in figure 17.2.

PB09 (input/output)/

CE2A (output)

PB08 (input/output)/

CS6B (output)/CE1B (output)

PB07 (input/output)/

CE2B (output)

PB06 (input/output)/

ICIOWR (output)

PB05 (input/output)/

ICIORD (output)

PB02 (input/output)/CKE (output)

PB03 (input/output)/

CAS (output)

PB04 (input/output)/

RAS (output)

PB01 (input/output)/

IOIS16 (input)

PB00 (input/output)/

WAIT (input)

PB10 (input/output)/

CS5B (output)/CE1A (output)

PB11 (input/output)/

CS4 (output)

PB12 (input/output)/

CS3 (output)

PB13 (input/output)/

BS (output)

Port B

Figure 17.2 Port B

17.2.1

Port B is a 14-bit I/O port that has a following register. For details on the address of this register

and the states of this register in each processing state, see section 20, List of Registers.

• Port B data register L (PBDRL)

17.2.2

Port B Data Register L (PBDRL)

PBDRL is a 16-bit readable/writable register which stores data for port B. Bits PB13DR to

PB0DR correspond to pins PB13 to PB00. (Description of multiplexed functions is omitted.)

When the pin function is general output port, if the value is written to PBDRL, the value is output

from the pin; if PBDRL is read, the value written to the register is directly read regardless of the

pin state.

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