HD6417618 datasheet(369/646 Pages) RENESAS

369 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 337 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

CKE1

CKE0

R/W

Clock Enable 1 and 0

Select the SCIF clock source and enable or disable

clock output from the SCK pin. Depending on the

combination of CKE1 and CKE0, the SCK pin can be

used for serial clock output or serial clock input.

The CKE0 setting is valid only when the SCIF is

operating on the internal clock (CKE1

= 0). The CKE0

setting is ignored when an external clock source is

selected (CKE1

= 1). In synchronous mode, select the

SCIF operating mode in the serial mode register

(SCSMR), then set CKE1 and CKE0.

• Asynchronous mode

00: Internal clock, SCK pin used for input pin (The input

signal is ignored. The state of the SCK pin depends

on both the SCKIO and SCKDT bits.)

01: Internal clock, SCK pin used for clock output

(The output clock frequency is 16 times the bit rate.)

10: External clock, SCK pin used for clock input

(The input clock frequency is 16 times the bit rate.)

11: Setting prohibited

• Synchronous mode

00: Internal clock, SCK pin used for serial clock output

01: Internal clock, SCK pin used for serial clock output

10: External clock, SCK pin used for serial clock input

11: Setting prohibited

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