STM32H562II datasheet(212/270 Pages) STMICROELECTRONICS

212 / 270 page

Electrical characteristics

STM32H562xx and STM32H563xx

212/270

DS14258 Rev 5

IDDV(DAC)

DAC consumption from

VREF+

DAC output buffer

No load,

middle

code

(0x800)

-170

µA

No load,

worst code

(0xF1C)

-170

DAC output buffer

OFF

No load,

middle/

worst code

(0x800)

-160

Sample and Hold mode, buffer ON,

CSH = 100 nF (worst code)

170*TON/

(TON+TOFF)(5)

Sample and Hold mode, buffer

OFF, CSH = 100 nF (worst code)

160*TON/

(TON+TOFF)(5)

1. Specified by design - Not tested in production, unless otherwise specified.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

3. DACx_OUT pin is not connected externally (internal connection only).

4. Refer to Table 58.

5. TON is the refresh phase duration, TOFF is the hold phase duration. Refer to the reference manual for more details.

Table 98. DAC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 99. DAC accuracy(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DNL

Differential non

linearity(2)

DAC output buffer ON

−2-

LSB

DAC output buffer OFF

−2-

Monotonicity

10 bits

INL

Integral non linearity(3)

DAC output buffer ON,

CL≤50 pF, RL≥5 kΩ

−4-

LSB

DAC output buffer OFF,

CL ≤ 50 pF, no RL

−4-

Offset

Offset error at code

0x800 (3)

DAC output buffer ON,

CL≤50 pF, RL ≥5 kΩ

VREF+ = 3.6 V

±12

VREF+ = 1.8 V

±25

DAC output buffer OFF,

CL ≤ 50 pF, no RL

±8

Offset1

Offset error at code

0x001(4)

DAC output buffer OFF,

CL ≤ 50 pF, no RL

±5

OffsetCal

Offset error at code

0x800 after factory

calibration

DAC output buffer ON,

CL≤50 pF, RL ≥5 kΩ

VREF+ = 3.6 V

±5

VREF+ = 1.8 V

±7

STM32H562II Datasheet(PDF) 212 Page - STMicroelectronics

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