STM32H562II datasheet(26/270 Pages) STMICROELECTRONICS

26 / 270 page

Functional overview

STM32H562xx and STM32H563xx

26/270

DS14258 Rev 5

The GTZC main features are:

•

Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB

•

MPCBB and TZIC accessible only with secure transactions

–

Enable illegal access events that may trigger a secure interrupt

•

Secure and nonsecure access supported for privileged/non-privileged part of TZSC

•

Set of registers to define product security settings:

–

Secure/privilege regions for external memories

–

Secure/privilege access mode for securable peripherals

–

Secure/privilege access mode for securable legacy masters

3.9

TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security attribution unit) and IDAU

(implementation defined attribution unit) define the access permissions based on secure

and nonsecure state.

•

SAU: up to eight SAU configurable regions are available for security attribution.

•

IDAU: It provides a first memory partition as nonsecure or nonsecure callable

attributes. It is then combined with the results from the SAU security attribution and the

higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs and peripherals

memory space is aliased twice for secure and nonsecure states. However, the external

memories space is not aliased.

3.9.1

TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-

aware type as follows:

•

securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to

define security properties

•

TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing

a specific TrustZone behavior such as a subset of registers being secure

3.9.2

Default TrustZone security state

The default system security state is detailed below:

•

CPU:

–

Cortex-M33 is in secure state after reset. The boot address must be in secure

address.

•

Memory map:

–

SAU is fully secure after reset. Consequently, all memory map is fully secure. Up

to eight SAU configurable regions are available for security attribution.

•

Flash memory:

–

Flash memory security area is defined by watermark user options.

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