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STM32H562II Datasheet(PDF) 38 Page - STMicroelectronics

Part # STM32H562II
Description  Arm® Cortex®-M33 32-bit MCU TrustZone® FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
PDF  270 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H562II Datasheet(HTML) 38 Page - STMicroelectronics

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Functional overview
STM32H562xx and STM32H563xx
38/270
DS14258 Rev 5
3.18
Cyclic redundancy check calculation unit (CRC)
The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.
3.19
CORDIC coprocessor (CORDIC)
The CORDIC coprocessor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
The CORDIC main features are:
•
24-bit CORDIC rotation engine
•
Circular and hyperbolic modes
•
Rotation and vectoring modes
•
Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural
logarithm
•
Programmable precision
•
Low-latency AHB slave interface
•
Results can be read as soon as ready without polling or interrupt
•
DMA read and write channels
•
Multiple register read/write by DMA
3.20
Filter math accelerator (FMAC)
The FMAC performs arithmetic operations on vectors. It comprises a multiplier/accumulator
(MAC) unit, together with address generation logic that allows it to index vector elements
held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be done.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
•
16 x 16-bit multiplier
•
24 + 2-bit accumulator with addition and subtraction
•
16-bit input and output data



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