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STM32H562II Datasheet(PDF) 43 Page - STMicroelectronics

Part # STM32H562II
Description  Arm® Cortex®-M33 32-bit MCU TrustZone® FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
PDF  270 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H562II Datasheet(HTML) 43 Page - STMicroelectronics

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DS14258 Rev 5
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STM32H562xx and STM32H563xx
Functional overview
62
calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.
The digital interface supports the following features:
•
One DAC interface, maximum two output channels
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave and triangular-wave generation
•
Sawtooth wave generation
•
Dual DAC channel for independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
Double data DMA capability to reduce the bus activity
•
External triggers for conversion
•
DAC output channel buffered/unbuffered modes
•
Buffer offset calibration
•
Each DAC output can be disconnected from the DAC_OUTx output pin
•
DAC output connection to on chip peripherals
•
Sample and Hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
•
Voltage reference input
3.27
Voltage reference buffer (VREFBUF)
The devices embed a voltage reference buffer that can be used as reference for ADCs and
DACs, and also as reference for external components through the VREF+ pin.
The internal voltage reference buffer supports three voltages: 1.8, 2.048, and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
3.28
Digital camera interface (DCMI)
The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG). It can be
used with black and white cameras, X24 and X5 cameras (it is assumed that all
preprocessing such as resizing is performed in the camera module).
Main features:
•
8-, 10-, 12-, or 14-bit parallel interface
•
Embedded/external line and frame synchronization
•
Continuous or snapshot mode
•
Crop feature
•
Support of the following data formats:



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