STM32H562II datasheet(35/270 Pages) STMICROELECTRONICS

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DS14258 Rev 5

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STM32H562xx and STM32H563xx

Functional overview

by user software. For faster lock-in during startup, automatic and manual trimming actions

can be combined.

3.14

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

After reset, all GPIOs are in analog mode to reduce power consumption.

If needed, the I/Os alternate function configuration can be locked following a specific

sequence, to avoid spurious writing to the I/Os registers.

Ten I/Os (PD6, PD7, PG9:14, PB8, PB9) can be independently supplied by a dedicated

VDDIO supply.

3.14.1

GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O

pin is configured as secure, its corresponding configuration bits for alternate function, mode

selection, I/O data are secure against a nonsecure access. The associated registers bit

access is restricted to a secure software only. After reset, all GPIO ports are secure.

3.15

Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, GPDMA2,

SDMMC1, SDMMC2, Ethernet) and the slaves (flash memory, FMC, OCTOSPI, SRAMs,

AHB and APB) peripherals. It ensures seamless and efficient operation, even when several

high-speed peripherals work simultaneously.

3.16

General purpose direct memory access controller (GPDMA)

The GPDMA controller is a bus master and system peripheral. It used to perform

programmable data transfers between memory-mapped peripherals and/or memories via

linked-lists, upon the control of an off-loaded CPU. The GPDMA main features are:

•

Dual bidirectional AHB master

•

Memory-mapped data transfers from a source to a destination:

–

Peripheral-to-memory

–

Memory-to-peripheral

–

Memory-to-memory

–

Peripheral-to-peripheral

•

Autonomous data transfers during Sleep mode

•

Transfers arbitration based on a four-grade programmed priority at a channel level:

–

One high-priority traffic class, for time-sensitive channels (queue 3)

–

Three low-priority traffic classes, with a weighted round-robin allocation for non

time-sensitive channels (queues 0, 1, 2)

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