STM32H562II datasheet(27/270 Pages) STMICROELECTRONICS

27 / 270 page

DS14258 Rev 5

27/270

STM32H562xx and STM32H563xx

Functional overview

–

Flash memory block based area is nonsecure after reset.

•

SRAMs:

–

All SRAMs are secure after reset. MPCBB (memory protection block based

controller) is secure.

•

External memories:

–

FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection

watermark based controller) is secure.

•

Peripherals

–

Securable peripherals are nonsecure after reset.

–

TrustZone-aware peripherals are nonsecure after reset. Their secure configuration

registers are secure.

•

All GPIOs are secure after reset.

•

Interrupts:

–

NVIC: All interrupts are secure after reset. NVIC is banked for secure and

nonsecure state.

•

TZIC: All illegal access interrupts are disabled after reset.

3.10

Power supply management

The power controller (PWR) main features are:

•

Power supplies and supply domains

–

Core domain (VCORE)

–VDD domain

–

Backup domain (VBAT)

–

Analog domain (VDDA)

–

SMPS power stage (VDDSMPS, available only on SMPS packages)

–VDDIO2 domain

–VDDUSB for USB transceiver

•

System supply voltage regulation

–

SMPS step down converter

–

Voltage regulator (LDO)

•

Power supply supervision

–

POR/PDR monitor

–

BOR monitor

–PVD monitor

•

Power management

–

Operating modes

–

Voltage scaling control

–

Low-power modes

•

VBAT battery charging

•

TrustZone security and privileged protection

STM32H562II Datasheet(PDF) 27 Page - STMicroelectronics

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