STM32H562II datasheet(23/270 Pages) STMICROELECTRONICS

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DS14258 Rev 5

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STM32H562xx and STM32H563xx

Functional overview

Note:

The ECC is supported by SRAM2, SRAM3, and BKPSRAM when enabled with the

SRAM2_ECC, SRAM3_ECC, and BKPRAM_ECC user option bits.

3.5.1

SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1,

SRAM2, SRAM3, can be programmed as secure or nonsecure by blocks, using the MPCBB

(block-based memory protection controller).

The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions

can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone

security controller) in the GTZC (global TrustZone controller).

3.5.2

SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, can be programmed as privileged or non-privileged by

blocks, using the MPCBB. The granularity of SRAM privilege block based is a page of

512 bytes. Backup SRAM regions can be programmed as privileged or non-privileged with

watermark, using the TZSC (TrustZone security controller) in the GTZC (global TrustZone

controller).

3.6

Security overview

The STM32H562xx and STM32H563xx security enables the possibility to reopen the debug

mode even if the product is in secure state.

The reopening of the debug mode is controlled with a debug authentication procedure which

permits the authentication of the host.

Sensible assets (such as keys or secret codes) must be protected when opening the debug

mode. The protection is made via code protection and hardware keys storage solutions

where all root of trust can be protected thanks to hardware mechanisms.

In cases where sensitive information cannot be protected, a partial or a full regression can

be launched to start a debug. Regressions are enabled by a debug authentication method.

Developers can introduce their own root of trust solution (OEM-iROT), including their

installation in a non-trusted environment, thanks to a secure firmware install (SFI) solution.

The boot stages are isolated via a hardware mechanism called HDPL (temporal isolation

level). The HDPL guarantees isolation of the different boot stages: ST assets, iROT

(immutable root of trust), uROT (updatable root of trust), secure operating system and

nonsecure applications.

The devices embed a hardware key storage solution with a dedicated flash memory area

per boot stages with access-control based on HDPL, which can be secure or nonsecure.

STM32H562xx and STM32H563xx are powered by an Arm Cortex-M33 core, associated

with all the TrustZone isolation infrastructure. This design permits to benefit from a run time

isolation to run secure applications.

STM32H562II Datasheet(PDF) 23 Page - STMicroelectronics

STM32H562II Datasheet(HTML) 23 Page - STMicroelectronics

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