STM32H562II datasheet(211/270 Pages) STMICROELECTRONICS

211 / 270 page

DS14258 Rev 5

211/270

STM32H562xx and STM32H563xx

Electrical characteristics

238

tSETTLING

Settling time (full scale: for a

12-bit code transition

between the lowest and the

highest input codes when

DAC_OUT reaches the final

value of ±0.5LSB, ±1LSB,

±2LSB, ±4LSB, ±8LSB)

Normal mode, DAC

output buffer ON,

CL ≤ 50 pF,

RL ≥ 5 kΩ

±0.5 LSB

2.05

µs

±1 LSB

1.97

2.87

±2 LSB

1.67

2.84

±4 LSB

1.66

2.78

±8 LSB

1.65

2.7

Normal mode, DAC output buffer

OFF, ±1LSB CL= 10 pF

-1.7

tWAKEUP

(2)

Wake-up time from off state

(setting the ENx bit in the

DAC control register) until

the final value of ±1LSB is

reached

Normal mode, DAC output buffer

ON, CL ≤ 50 pF, RL = 5 kΩ

-5

7.5

µs

Normal mode, DAC output buffer

OFF, CL ≤ 10 pF

-2

PSRR

DC VDDA supply rejection

ratio

Normal mode, DAC output buffer

ON, CL ≤ 50 pF, RL = 5 kΩ

--80

-28

tSAMP

Sampling time in Sample

and Hold mode, CL= 100 nF

(code transition between the

lowest and the highest input

code when DAC_OUT

reaches the ±1LSB final

value)

MODE<2:0>_V12 = 100/101

(BUFFER ON)

-0.7

2.6

MODE<2:0>_V12 = 110

(BUFFER OFF)

11.5

18.7

MODE<2:0>_V12=111(3)

(INTERNAL BUFFER OFF)

-0.3

0.6

µs

Ileak

Output leakage current

(4)

CIint

Internal sample and hold

capacitor

1.8

2.2

2.6

tTRIM

Middle code offset trim time Minimum time to verify each code

µs

Voffset

Middle code offset for

1 trim code step

VREF+ = 3.6 V

850

µV

VREF+ = 1.8 V

425

IDDA(DAC)

DAC quiescent consumption

from VDDA

DAC output buffer

No load,

middle

code

(0x800)

-360

µA

No load,

worst code

(0xF1C)

-490

DAC output buffer

OFF

No load,

middle/

worst code

(0x800)

-20

Sample and Hold mode,

CSH = 100 nF

360*TON/

(TON+TOFF)(5)

Table 98. DAC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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