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STM32H562II Datasheet(PDF) 201 Page - STMicroelectronics |
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STM32H562II Datasheet(HTML) 201 Page - STMicroelectronics |
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201 / 270 page ![]() DS14258 Rev 5 201/270 STM32H562xx and STM32H563xx Electrical characteristics 238 Table 93. PSSI transmit characteristics(1) Symbol Parameter Conditions Min Max Unit - Frequency ratio PSSI_PDCK/fHCLK -- 0.4 - PSSI_PDCK PSSI clock input 2.7 V ≤ VDD ≤ 3.6 V - 90(2) MHz 1.71 V ≤ VDD ≤ 3.6 V - 86 Dpixel PSSI clock input duty cycle 30 70 % tov(DATA) Data output valid time 2.7 V ≤ VDD ≤ 3.6 V - 11 ns 1.71 V ≤ VDD ≤ 3.6 V - 11.5 toh(DATA) Data output hold time 1.71 V ≤ VDD ≤ 3.6 V 5.5 - tov((DE) DE output valid time - 11.5 toh(DE) DE output hold time 5.5 - tsu(RDY) RDY input setup time 0.5 - th(RDY) RDY input hold time 0.5 - 1. Evaluated by characterization - Not tested in production. 2. This maximal frequency does not consider receiver setup and hold timings. Table 94. PSSI receive characteristics(1) Symbol Parameter Conditions Min Max Unit - Frequency ratio PSSI_PDCK/fHCLK -0.4 - PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 100 MHz Dpixel PSSI clock input duty cycle - 30 70 % tsu(DATA) Data input setup time 1.71 V ≤ VDD ≤ 3.6 V 2- ns th(DATA) Data input hold time 2.5 - tsu((DE) DE input setup time 1.5 - th(DE) DE input hold time 2 - tov(RDY) RDY output valid time - 16.5 toh(RDY) RDY output hold time 5.5 - 1. Evaluated by characterization - Not tested in production. |
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