STM32H562II datasheet(197/270 Pages) STMICROELECTRONICS

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DS14258 Rev 5

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STM32H562xx and STM32H563xx

Electrical characteristics

238

Table 90. OCTOSPI characteristics in DTR mode (with DQS) / HyperBus(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FCLK

OCTOSPI clock frequency

1.71 V < VDD < 1.9 V,

CL = 15 pF

125(3)(4)

MHz

2.7 V < VDD < 3.6 V,

CL = 15 pF

125(3)(5)

tw(CLKH)

OCTOSPI clock

high and low time

PRESCALER[7:0] = n

= (0, 1, 3, 5, …, 255)

t(CLK)/2 - 0.5

t(CLK)/2 + 0.5

tw(CLKL)

t(CLK)/2 - 0.5

t(CLK)/2 + 0.5

tw(CLKH)

OCTOSPI clock

high and low time

PRESCALER[7:0] = n

= (2, 4, 6, 8, …, 254)

(n/2)*t(CLK)/

(n+1) - 0.5

(n/2)*t(CLK)/

(n+1) + 0.5

tw(CLKL)

(n/2+1)*t(CLK)/

(n+1) - 0.5

(n/2+1)*t(CLK)/

(n+1) + 0.5

tv(CLK)

Clock valid time

t(CLK) + 2

th(CLK)

Clock hold time

t(CLK)/2 - 1

tODr(CLK)(5)

CLK, NCLK crossing level

on CLK rising edge

VDD = 1.8 V

890

1300

tODf(CLK)(5)

CLK, NCLK crossing level

on CLK falling edge

VDD = 1.8 V

790

1080

tw(CS)

Chip select high time

3 * t(CLK)

tv(DQ)

Data input valid time

tv(DS)

Data strobe input valid time

th(DS)

Data strobe input hold time

tv(RWDS)

Data strobe output valid time

3 * t(CLK)

tsr(DQ),

tsf(DQ)

Data input setup time

-0.5

thr(DQ),

thf(DQ)

Data input hold time

tvr(OUT)

tvf(OUT)

Data output valid time

DHQC = 0

2.5

3.5

DHQC = 1, all

prescaler values

except 0

t(CLK)/4

+ 0.5

t(CLK)/4 + 1

thr(OUT)

thf(OUT)

Data output hold time

DHQC = 0

1.5

DHQC = 1, all

prescaler values

except 0

t(CLK)/4 - 1

1. Evaluated by characterization - Not tested in production.

2. Delay block activated.

3. Maximum frequency value are given for a maximum RWDS to DQ skew of ± 1.0 ns.

4. DHQC must be set to reach the mentioned frequency.

5. It is recommended that PF10/PB5, PB4/PB5 and PA3/PB5 are in line with crossing specification.

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