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STM32H562II Datasheet(PDF) 200 Page - STMicroelectronics

Part # STM32H562II
Description  Arm® Cortex®-M33 32-bit MCU TrustZone® FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
PDF  270 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H562II Datasheet(HTML) 200 Page - STMicroelectronics

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Electrical characteristics
STM32H562xx and STM32H563xx
200/270
DS14258 Rev 5
Figure 52. DCMI timing diagrams
5.3.22
PSSI interface characteristics
Unless otherwise specified, the parameters given in Table 92 and Table 93 are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 20 and Section 5.3.1, with the following configuration:
•
PSSI_PDCK polarity: falling
•
PSSI_RDY and PSSI_DE polarity: low
•
Bus width: 16 lines
•
DATA width: 32 bits
•
Capacitive load CL= 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling VOS0 selected
Table 92. DCMI characteristics(1)
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
-
0.4
-
DCMI_PIXCLK
Pixel clock input
-
100
MHz
DPIXEL
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
2.5
-
ns
th(DATA)
Data hold time
2
-
tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times
2.5
-
th(HSYNC), th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times
1.5
-
1. Evaluated by characterization - Not tested in production.
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)



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