STM32H562II datasheet(204/270 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H562xx and STM32H563xx

204/270

DS14258 Rev 5

RAIN(6)

External input

impedance

Resolution = 12 bits, TJ = 130°C (tolerance 4 LSBs)

321

Ω

Resolution = 12 bits, TJ = 125°C

220

Resolution = 10 bits, TJ = 130°C

1039

Resolution = 10 bits, TJ = 125°C

2100

Resolution = 8 bits, TJ = 130°C

6327

Resolution = 8 bits, TJ = 125°C

12000

Resolution = 6 bits, TJ = 130°C

47620

Resolution = 6 bits, TJ = 125°C

80000

CADC

Internal

sample and

hold capacitor

tADCVREG_

STUP

LDO startup

time

µs

tSTAB

Power-up time

LDO already started

Conversion

cycle

tOFF_CAL

Offset

calibration time

1335

1/fadc_ker_ck

tLATR

Trigger

conversion

latency for

regular and

injected

channels

without

aborting the

conversion

CKMODE = 00

1.5

2.5

CKMODE = 01

2.5

CKMODE = 10

2.5

CKMODE = 11

2.25

tLATRINJ

Trigger

conversion

latency for

regular and

injected

channels when

a regular

conversion is

aborted

CKMODE = 00

2.5

3.5

CKMODE = 01

3.5

CKMODE = 10

3.5

CKMODE = 11

3.25

Sampling time

2.5

640.5

tCONV

Total

conversion

time (including

sampling)

N-bits resolution

tS + 0.5

+ N

IDDA_D(ADC)

Consumption

on VDDA and

VREF,

differential

mode

fs = 5 MSPS

600

µA

fs = 1 MSPS

190

fs = 0.1 MSPS

IDDA_SE(ADC)

Consumption

on VDDA and

VREF, single-

ended mode

fs = 5 MSPS

500

fs = 1 MSPS

150

fs = 0.1 MSPS

IDD(ADC)

Consumption

on VDD

fadc_ker_ck = 75 MHz

265

fadc_ker_ck = 50 MHz

175

fadc_ker_ck = 25 MHz

fadc_ker_ck = 12.5 MHz

fadc_ker_ck = 6.25 MHz

fadc_ker_ck = 3.125 MHz

1. Specified by design - Not tested in production.

2. The voltage booster on ADC switches must be used for VDDA < 2.7 V (embedded I/O switches).

Table 95. 12-bit ADC characteristics(1)(2) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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