STM32H562II datasheet(199/270 Pages) STMICROELECTRONICS

199 / 270 page

DS14258 Rev 5

199/270

STM32H562xx and STM32H563xx

Electrical characteristics

238

Figure 51. OCTOSPI HyperBus write

5.3.20

Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 91 are derived from tests

performed under the ambient temperature, fHCLK frequency and VDD supply voltage

summarized in Table 20, with the following configuration:

5.3.21

DCMI interface characteristics

Unless otherwise specified, the parameters given in Table 92 are derived from tests

performed under the ambient temperature, fHCLK frequency and VDD supply voltage

summarized in Table 20, with the following configuration:

•

DCMI_PIXCLK polarity: falling

•

DCMI_VSYNC and DCMI_HSYNC polarity: high

•

Data formats: 14 bits

•

Capacitive load CL = 30 pF

•

Measurement points done at CMOS levels: 0.5 VDD

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling VOS0 selected

MSv47734V3

NCS

Access latency

Latency count

Command address

47:40

39:32

31:24

23:16

15:8

7:0

Dn+1

Host drives DQ[7:0] and the memory drives RWDS.

Host drives DQ[7:0] and RWDS.

CLK, NCLK

RWDS

DQ[7:0]

tw(CS)

tv(RWDS)

tv(CLK)

th(CLK)

High = 2x latency count

Low = 1x latency count

Read write recovery

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

Table 91. Delay block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tinit

Initial delay

750

1100

1700

t∆

Unit delay

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