STM32H562II datasheet(160/270 Pages) STMICROELECTRONICS

160 / 270 page

Electrical characteristics

STM32H562xx and STM32H563xx

160/270

DS14258 Rev 5

limit (higher than 5 LSB TUE), out of conventional limits (-5 / +0 µA range) of induced

leakage current on adjacent pins, or other functional failures (such as reset, oscillator

frequency deviation).

The following table shows I/Os current injection susceptibility data. Negative/positive

induced leakage currents are caused, respectively, by negative/positive injection.

5.3.15

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 58 are derived from tests

performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL

compliant (except for BOOT0).

Note:

For information on GPIO configuration, refer to AN4899 “STM32 GPIO configuration for

hardware settings and low-power consumption”, available on www.st.com.

Table 57. I/O current injection susceptibility(1)

1. Evaluated by characterization - Not tested in production.

Symbol

Description

Functional susceptibility

Unit

Negative

injection

Positive

injection

IINJ

Injected current on pins PA4, PA5, PB2, PB12,

PC14, PC15, PD8, and PH2

Injected current on all other pins

N/A

Table 58. I/O static characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

I/O input low level voltage

except BOOT0

1.08 V < VDD < 3.6 V

0.3 VDDIOx(2)

I/O input low level voltage

except BOOT0

0.4 VDDIOx - 0.1(3)

BOOT0 I/O input low level

voltage

0.19 VDDIOx + 0.1(3)

VIH

I/O input high level

voltage except BOOT0

1.08 V < VDD < 3.6 V

0.7 VDDIOx(2)

I/O input high level

voltage except BOOT0

0.52 VDDIOx +

0.18(3)

BOOT0 I/O input high

level voltage

0.17 VDDIOx +

0.6(3)

VHYS(3)

TT_xx, FT_xxx and NRST

I/O input hysteresis

1.08 V < VDD < 3.6 V

250

BOOT0 I/O input

hysteresis

1.71 V < VDD < 3.6 V

200

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