STM32H562II datasheet(148/270 Pages) STMICROELECTRONICS

148 / 270 page

Electrical characteristics

STM32H562xx and STM32H563xx

148/270

DS14258 Rev 5

Figure 27. High-speed external clock source AC timing diagram

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal must respect the Table 41 in addition to Table 58. The external

clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the

clock squarer must be activated (refer to RM0481).

Visw(HSEH)

(VHSEH -VHSEL)(3)

Analog low-swing

OSC_IN peak-to-peak

amplitude

External analog low

swing clock

0.2

2/3 VDD

DuCyHSE

Analog low-swing

OSC_IN duty cycle

tr(HSE) / tf(HSE)

Analog low-swing

OSC_IN rise and fall

times

External analog low

swing clock, 10% to 90%

0.05 / fHSE_ext

0.3 / fHSE_ext ns

1. Specified by design - Not tested in production..

2. The rise and fall times for a digital input signal are not specified, but the VHSEH and VHSEL conditions must be fulfilled

anyway.

3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.

Table 40. High-speed external user clock characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ai17528b

OSC_IN

External

STM32

clock source

VHSEH

tf(HSE)

tW(HSE)

90 %

10 %

THSE

tr(HSE)

tW(HSE)

fHSE_ext

VHSEL

Table 41. Low-speed external user clock characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fLSE_ext

User external clock source

frequency

External digital/analog clock

32.768

1000

kHz

VLSEH

Digital OSC32_IN input

high-level voltage

External digital clock

0.7 VDD

-VDD

VLSEL

Digital OSC32_IN input

low-level voltage

VSS

-0.3 VDD

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