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STM32H562II Datasheet(PDF) 136 Page - STMicroelectronics |
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STM32H562II Datasheet(HTML) 136 Page - STMicroelectronics |
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136 / 270 page ![]() Electrical characteristics STM32H562xx and STM32H563xx 136/270 DS14258 Rev 5 • All peripherals are disabled except when explicitly mentioned. • The flash memory access time is adjusted with the minimum wait-state number, depending on the fHCLK frequency (refer to the tables “FLASH recommended number of wait states and programming delay” available in the reference manual). • When the peripherals are enabled, the AHB clock frequency is the CPU frequency and the APB clock frequency is AHB frequency. The parameters given in the following tables are derived from tests performed under supply voltage conditions summarized in Table 20, and, unless otherwise specified, at ambient temperature. The maximum current consumption is given for LDO regulator ON. Table 28. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, 2-way instruction cache ON, PREFETCH ON Symbol Parameter Conditions fHCLK (MHz) Typ LDO Typ SMPS Max(1)(2) Unit TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 130 °C IDD(Run) Supply current in Run mode All peripherals disabled VOS0 250 32.1 17.5 37 65 87 - mA 215 27.9 15.0 32 60 82 - 200 25.7 13.8 30 59 81 - VOS1 200 22.1 11.0 25 45 62 93 180 20.3 10.1 23 43 59 90 168 18.8 9.3 21 42 58 89 150 16.9 8.5 20 40 56 88 VOS2 150 15.4 7.4 17 33 47 73 100 10.8 5.2 13 28 41 68 VOS3 100 9.8 4.5 11 23 34 55 60 6.4 3.0 8.0 20 30 52 25 3.2 1.7 5.0 17 27 49 All peripherals enabled VOS0 250 86.8 49.8 90 118 140 - 215 75.0 43.2 78 107 128 - 200 69.5 40.1 72 102 123 - VOS1 200 60.7 31.7 62 82 99 130 180 55.1 28.5 56 76 92 124 150 45.8 23.4 47 68 84 116 VOS2 150 41.9 20.0 43 59 72 98 100 28.5 13.8 30 45 58 85 VOS3 100 25.9 11.7 27 39 49 71 60 16.2 7.5 17 29 40 61 25 7.5 3.8 9.0 21 31 53 |
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