STM32H562II datasheet(231/270 Pages) STMICROELECTRONICS

231 / 270 page

DS14258 Rev 5

231/270

STM32H562xx and STM32H563xx

Electrical characteristics

238

Figure 70. SAI slave timing waveforms

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 122 and Table 123 are derived

from tests performed under the ambient temperature, fPCLKx frequency and VDD supply

voltage summarized in Table 20, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load CL= 30 pF

•

Measurement points are done at CMOS levels: 0.5 VDD

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

Refer to Section 5.3.15 for more details on the input/output characteristics.

MS32772V2

SAI_SCK_X

(CKSTR = 1)

SAI_FS_X

(input)

SAI_SD_X

(transmit)

tsu(FS)

Slot n

SAI_SD_X

(receive)

tw(CKH_X)

th(FS)

Slot n+2

tv(SD_ST)

th(SD_ST)

Slot n

tsu(SD_SR)

tw(CKL_X)

th(SD_SR)

1/fSCK

SAI_SCK_X

(CKSTR = 0)

Table 122. Dynamic characteristics: SD/MMC, VDD = 2.7 to 3.6 V(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPP

Clock frequency in data transfer mode

130(2)/6(3) MHz

tW(CKL) Clock low time

fPP = 52 MHz

8.5

9.5

tW(CKH) Clock high time

8.5

9.5

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode

tISU

Input setup time HS

tIH

Input hold time HS

tIDW(5) Input valid window (variable window)

4.5

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) mode

tOV

Output valid time HS

5.5/38(3)

tOH

Output hold time HS

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