Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

STM32H562II Datasheet(PDF) 220 Page - STMicroelectronics

Part # STM32H562II
Description  Arm® Cortex®-M33 32-bit MCU TrustZone® FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
PDF  270 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H562II Datasheet(HTML) 220 Page - STMicroelectronics

Back Button STM32H562II Datasheet HTML 216Page - STMicroelectronics STM32H562II Datasheet HTML 217Page - STMicroelectronics STM32H562II Datasheet HTML 218Page - STMicroelectronics STM32H562II Datasheet HTML 219Page - STMicroelectronics STM32H562II Datasheet HTML 220Page - STMicroelectronics STM32H562II Datasheet HTML 221Page - STMicroelectronics STM32H562II Datasheet HTML 222Page - STMicroelectronics STM32H562II Datasheet HTML 223Page - STMicroelectronics STM32H562II Datasheet HTML 224Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 220 / 270 page
background image
Electrical characteristics
STM32H562xx and STM32H563xx
220/270
DS14258 Rev 5
Table 112. USART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCK
USART clock frequency
Master receiver
1.71 V < VDD < 3.6 V
--
31
MHz
Master transmitter
1.71 V < VDD < 3.6 V
31/6(2)
Master transmitter
2.7 V < VDD < 3.6 V
31/6(2)
Slave receiver
1.71 V < VDD < 3.6 V
83
Slave transmitter
1.71 V < VDD < 3.6 V
32/6(2)
Slave transmitter
2.7 V < VDD < 3.6 V
35/6(2)
tsu(NSS)
NSS setup time
Slave mode
tker(3) + 3.5
-
-
ns
th(NSS)
NSS hold time
Slave mode
2.5
-
-
tw(SCKH)
tw(SCKL)
CK high and low time
Master mode
1/fck/2 -1
1/fck/2
1/fck/2 +1
tsu(RX)
Data input setup time
Master mode
13
-
-
Slave mode
3.5
-
-
th(RX)
Data input hold time
Master mode
0.5
-
-
Slave mode
1.5
-
-
tv(TX)
Data output valid time
Slave mode,
1.71 V < VDD < 3.6 V
-
11.5
15.5/71(2)
Slave mode,
2.7 V < VDD < 3.6 V
-
14/35(2)
Slave mode,
1.71 V < VDD < 3.6 V
-
2.5
3/52(2)
Slave mode,
2.7 V < VDD < 3.6 V
-3/22(2)
th(TX)
Data output hold time
Slave mode
7.5
-
-
ns
Master mode
0
-
-
1. Evaluated by characterization - Not tested in production.
2. For PB14 with OSPEEDRy[1:0] = 01.
3. Tker is the usart_ker_ck_pres clock period.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link to Datasheet   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com