STM32H562II datasheet(222/270 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H562xx and STM32H563xx

222/270

DS14258 Rev 5

The parameters given in Table 113 are obtained with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0

The timings are in line with MIPI specification, except for the ones given in Table 113 and

Table 114. For tSU_OD and tSU_PP this can be mitigated by increasing the corresponding

SCL low duration in the I3C_TIMINGR0 register. For tSCO this can be mitigated by enabling

and adjusting the clock stall time both on the address ACK phase and on the data read Tbit

phase in the I3C_TIMINGR2 register. This can also be mitigated by increasing the SCL low

duration in the I3C_TIMINGR0 register. For further details refer to AN5879.

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 115 are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 20, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load CL = 30 pF

•

Measurement points are done at CMOS levels: 0.5 VDD

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0

Refer to Section 5.3.15 for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO for SPI).

Table 113. I3C open-drain measured timing

Symbol

Parameter

Conditions

I3C open drain mode

(specification)

Timing

measurements

Unit

Min

Max

tSU_OD

SDA data setup time

during open drain mode

Controller

1.71 V < VDD < 3.6 V

16.5

Table 114. I3C push-pull measured timing

Symbol

Parameter

Conditions

I3C open drain mode

(specification)

Timing

measurements

Unit

Min

Max

tSU_PP

SDA signal data setup in

push-pull mode

Controller

1.71 V < VDD < 3.6 V

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