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STM32H562II Datasheet(PDF) 192 Page - STMicroelectronics

Part # STM32H562II
Description  Arm® Cortex®-M33 32-bit MCU TrustZone® FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
PDF  270 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H562II Datasheet(HTML) 192 Page - STMicroelectronics

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Electrical characteristics
STM32H562xx and STM32H563xx
192/270
DS14258 Rev 5
•
For 2.7 V< VDD< 3.6 V: maximum FMC_SDCLK = 95 MHz at 20 pF (100 MHz for
VDD > 3.0V)
•
For 1.71 V < VDD < 1.8 V: maximum FMC_SDCLK = 95 MHz at 15 pF
•
For 1.71 V < VDD < 1.8 V: maximum FMC_SDCLK = 90 MHz at 20 pF
Figure 45. SDRAM read access waveforms (CL = 1)
MS32751V2
Row n
Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR)
td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Col2
Coli
Coln
Data2
Datai
Datan
Data1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS)
th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
Table 84. SDRAM read timings(1)
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck - 0.5 2Tfmc_ker_ck + 0.5
ns
tsu(SDCLKH _Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
0.5
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL- SDNE)
Chip select valid time
-
1.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
1. Evaluated by characterization - Not tested in production.



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