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T89C51RD2-RDTIL Datasheet(PDF) 47 Page - ATMEL Corporation

Part # T89C51RD2-RDTIL
Description  0 to 40 MHz Flash Programmable 8-bit Microcontroller
PDF  104 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

T89C51RD2-RDTIL Datasheet(HTML) 47 Page - ATMEL Corporation

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T89C51RD2
4243G–8051–05/03
Reset value XXXX X000
WDT During Power Down and
Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode the user does not need to service the WDT. There are 2 methods of
exiting Power Down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power Down mode. When Power Down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
T89C51RD2 is reset. Exiting Power Down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T89C51RD2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
If the WDT is activated, the power consumption in stand-by mode will be above the
specified value.
0
S0
WDT Time-out select bit 0
S2
S1
S0Selected Time-out
000(214 - 1) machine cycles, 16.3 ms @ 12 MHz
001(2
15 - 1) machine cycles, 32.7 ms @ 12 MHz
010(2
16 - 1) machine cycles, 65.5 ms @ 12 MHz
011(217 - 1) machine cycles, 131 ms @ 12 MHz
100(2
18 - 1) machine cycles, 262 ms @ 12 MHz
101(2
19 - 1) machine cycles, 542 ms @ 12 MHz
110(220 - 1) machine cycles, 1.05 s @ 12 MHz
111(2
21 - 1) machine cycles, 2.09 s @ 12 MHz
Bit
Number
Bit
Mnemonic
Description



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