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T89C51RD2-RDTIL Datasheet(PDF) 79 Page - ATMEL Corporation |
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T89C51RD2-RDTIL Datasheet(HTML) 79 Page - ATMEL Corporation |
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79 / 104 page  79 T89C51RD2 4243G–8051–05/03 Figure 32. Programming and Verification Signal’s Waveform Extra Memory Mapping The memory mapping the T89C51RD2 software registers in the Extra Flash memory is described in the table below. All other addresses are reserved Control signals Data In ALE/PROG A0-A15 Programming Cycle D0-D7 EA Data Out Read/Verify Cycle 5V 0V P2.7 48 clk (load latch ) or 10 ms (write) or 100 ms (erase) Table 42. Extra Row Memory Mapping (XAF) Address Default content Copy of device ID #3 0061h FFh Copy of device ID #2 0060h FCh Copy of device ID #1 0031h D7h Copy of Manufacturer Code: ATMEL 0030h 58h Software Security Byte (level 1 by default) 0005h FFh Copy of HSB (level 4 by default and BLJB = 0) 0004h 18h or 1Bh Software Boot Vector 0001h FCh Boot Status Byte 0000h FFh |
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