T89C51RD2-RDTIL datasheet(39/104 Pages) ATMEL

39 / 104 page

T89C51RD2

4243G–8051–05/03

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 23. IE Register

IE - Interrupt Enable Register (A8h)

Reset Value = 0000 0000b

Bit addressable

ET2

ET1

EX1

ET0

EX0

Bit

Number

Bit

Mnemonic Description

7EA

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its own interrupt enable bit.

6EC

PCA interrupt enable bit

Clear to disable . Set to enable.

5ET2

Timer 2 overflow interrupt Enable bit

Clear to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

4ES

Serial port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

3ET1

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

EX1

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

1ET0

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

EX0

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

T89C51RD2-RDTIL Datasheet(PDF) 39 Page - ATMEL Corporation

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