T89C51RD2-RDTIL datasheet(46/104 Pages) ATMEL

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T89C51RD2

4243G–8051–05/03

Hardware Watchdog

Timer

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer

ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable

the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location

0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator

is running and there is no way to disable the WDT except through reset (either hardware

reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH

pulse at the RST-pin.

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR

location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH

and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it

reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will

increment every machine cycle while the oscillator is running. This means the user must

reset the WDT at least every 16383 machine cycle. To reset the WDT the user must

write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter

cannot be read or written. When WDT overflows, it will generate an output RESET pulse

at the RST-pin. The RESET pulse duration is 96 x T

OSC , where TOSC = 1/FOSC . To

make the best use of the WDT, it should be serviced in those sections of code that will

periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 27 counter has been added to extend the Time-out

capability, ranking from 16ms to 2s @ F

OSC = 12MHz. To manage this feature, refer to

WDTPRG register description, Table 29. (SFR0A7h).

Table 28. WDTRST Register

WDTRST Address (0A6h)

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

Table 29. WDTPRG Register

WDTPRG Address (0A7h)

Reset value

Bit

Number

Bit

Mnemonic

Description

7T4

Reserved

The value read from this bit is undeterminated. Do not try to set this bit..

6T3

5T2

4T1

3T0

WDT Time-out select bit 2

WDT Time-out select bit 1

T89C51RD2-RDTIL Datasheet(PDF) 46 Page - ATMEL Corporation

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