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STM32H562II Datasheet(PDF) 236 Page - STMicroelectronics |
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STM32H562II Datasheet(HTML) 236 Page - STMicroelectronics |
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236 / 270 page  Electrical characteristics STM32H562xx and STM32H563xx 236/270 DS14258 Rev 5 Figure 75. Ethernet MII timing diagram Figure 76. Ethernet SMI timing diagram JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 127 and Table 128 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL= 30 pF • HSLV activated when VDD ≤ 2.7 V • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.15 for more details on the input/output characteristics: ai15668b MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER td(TXEN) td(TXD) tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK MII_TX_EN MII_TXD[3:0] MS31384V1 ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO) |
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