STM32H562II datasheet(124/270 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H562xx and STM32H563xx

124/270

DS14258 Rev 5

Caution:

Each power supply pair must be decoupled with filtering ceramic capacitors as shown

above. These capacitors must be placed as close as possible to or below the appropriate

pins on the underside of the PCB to ensure the good functionality of the device. It is not

recommended to remove filtering capacitors to reduce PCB size or cost. This might cause

incorrect operation of the device.

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 17, Table 18, and Table 19

may cause permanent damage to the device. These are stress ratings only and the

functional operation of the device at these conditions is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability. Device mission profile

(application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended

mission profiles are available on demand.

Table 17. Voltage characteristics(1)

Symbol

Ratings

Min

Max

Unit

VDDx - VSS

External main supply voltage (including

VDDSMPS(2), VDDA, VDDUSB, VDDIO2(2)(3)(4),

VBAT, and VREF+)

-0.3

4.0

VDDIOx(4) -

VSS

I/O supply when HSLV(2) = 0

-0.3

4.0

I/O supply when HSLV(2) = 1

-0.3

2.75

VIN(5)

Input voltage on FT_xxx pins except FT_c pins VSS - 0.3

min (min(VDD, VDDA, VDDUSB,

VDDIO2) + 4.0, 6.0 V)(6)(7)

Input voltage on FT_t in VBAT mode

VSS - 0.3

min (min(VBAT, VDDA, VDDUSB,

VDDIO2) + 4.0V, 6.0 V)

Input voltage on TT_xx pins

VSS - 0.3

4.0

Input voltage on BOOT0 pin

VSS

min (min(VDD, VDDA, VDDUSB,

VDDIO2) + 4.0, 6.0 V)(6)

Input voltage on FT_c pins

VSS - 0.3

5.5

Input voltage on any other pins

VSS - 0.3

4.0

VREF+-VDDA Allowed voltage difference for VREF+ > VDDA

-0.4

|∆VDDx|

Variations between different VDDX power pins

of the same domain

-50.0

|VSSx-VSS|

Variations between all the different ground pins

50.0

1. All main power (VDD, VDDA, VDDUSB, VDDIO2, VREF+, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always

be connected to the external power supply, in the permitted range.

2. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.

3. If HSLV = 0.

4. VDDIO1 or VDDIO2. VDDIO1 = VDD.

5. VIN maximum must always be respected. Refer to the maximum allowed injected current values.

6. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

7. This formula must be applied on power supplies related to the I/O structure described by the pin definition table.

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